![]() ![]() I thank you all in advance and look forward to any input, good or bad.īasic XOR gate block VHDL Code library ieee use ieee.std_logic_1164.all entity xor_gate is port( a: in std_logic b: in std_logic pari: in std_logic paro: out std_logic) end xor_gate architecture behavior of xor_gate is begin paro. ![]() I would like a second opinion to make sure I have written it correctly and if it will do what it is designed to do. My code is written such that a basic XOR block is then added as a component of the complete parity generator. The basic operation is to XOR the A and B inputs to perform an iterative process with an output of '1' as odd and an output of '0' as even. My problem is that I am trying to run a timing simulation to make sure it will work correctly but I am not sure what I should be looking for. I was finally able to compile it successfully. I have compiled it 10 times and worked out any bugs that it found. I have completed a VHDL 16-bit parity generator and I would like to know if I have programmed it correctly. Verilog Program For Odd Parity Generator.pdf Free Download Here VHDL Examples - California State University, Northridge. ![]()
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